Yu Yang Wang is currently an R&D Engineer Staff at Synopsys Inc, where they focus on signal integrity R&D, including HSPICE/FINESIM and S-parameter modeling. Previously, Yu worked as a Signal Integrity Engineer at Intel Corporation and served as a Staff Signal Integrity Engineer at Marvell Semiconductor, contributing to projects involving Serdes interface and DDR signal integrity. Yu began their career as a Design Engineer at IDT from 2006 to 2008. They earned a Bachelor of Science and a Doctor of Philosophy in Electrical and Electronics Engineering and Microwave Technology from Shanghai Jiao Tong University.
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