YUTING GAN

Yuting Gan is currently an ASIC Design Staff Engineer at Synopsys, involved in PCIe Subsystem Design and RTL coding for GEN6 compliance PIPE MUX logic. Previously, Yuting worked as an ASIC Design Sr. Engineer at BYD, contributing to the ADAS SOC NOC team by developing RTL coding for AXI bridges and Timestamp SYNC architectures. Yuting also served as an ASIC Design Engineer at Qualcomm Atheros, focusing on Wi-Fi MAC hardware design. Yuting earned a Bachelor’s degree in Electronic Science and Technology from Wuhan University of Technology and a Master's degree in Microelectronics Systems Design with Distinction from the University of Southampton.