Ales Dolinar

Ales Dolinar is a Senior FPGA Design Engineer at TASKING, specializing in FPGA design using VHDL and Verilog, with a strong background in Xilinx, Lattice, and Altera tools. Prior to their current role, Ales worked as a Senior FPGA Design Engineer at iSYSTEM from 2013 to 2023 and as an Embedded Hardware Design Engineer at Iskratel from 2006 to 2013. Ales holds a Master’s degree in Electrical Engineering from the Faculty of Electrical Engineering, earned between 1999 and 2006. Their expertise includes digital electronic circuit design, hardware architecture, and embedded software development in C and C++.