Georgios Tsiolis

Mixed Signal Design Engineer at Teledyne e2v

Georgios Tsiolis is a Mixed Signal Design Engineer at e2v since September 2015, following a role as an Analogue Design Engineer in the imaging division at STMicroelectronics from March 2012 to September 2015. Prior experience includes a University Thesis Project Design position at National Semiconductor from August 2010 to September 2011, where Georgios contributed to high precision clock design. Georgios holds an MSc in Microelectronics from Delft University of Technology (2009-2011) and a combined BSc and MSc in Electrical and Electronic Engineering from the National Technical University of Athens (2003-2009). Early education was completed at 4th High School Zografou (2001-2003).

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