Digeshkumar patel

Digeshkumar Patel has extensive experience in design verification and engineering, having held various roles at prominent organizations. Starting as a College Trainee at the Indian Space Research Organization in 2010, Digeshkumar contributed to the development of a Flash Memory Based Portable Data Acquisition System. Following this, a tenure at eInfochips allowed for growth into positions such as Senior Design Verification Engineer and Technical Lead from January 2017 to April 2019. Afterward, engagements at Arm as Staff Engineer and leadIC Design Pvt Ltd as Design Verification Lead transitioned into the current role as Design Verification Lead at Teradyne, which began in August 2024. Digeshkumar holds a Bachelor of Engineering in Electronics and Communication with Distinction from Parul Institute of Engineering and Technology, completed in 2010.