Karthikeyan Virchily Jyothiraman

Karthikeyan Virchily Jyothiraman is a Semiconductor Design Engineer at Teradyne since October 2021, with prior experience as a Lead Engineer at Synapse Design Inc., and as a Technical Lead at ARICENT N.A. INC. Karthikeyan has extensive expertise in low power design implementation, physical aware logic synthesis, and resolving complex design flow issues, contributing to successful end-to-end IP and ASIC SoC design. Previous roles include Technical Lead Engineer at Altran with exposure to various technologies and semiconductor industries, and a Senior Physical Design Engineer at Synapse Design Automation Inc., focusing on floorplanning, routing, and physical verification. Karthikeyan holds a Master’s in Technology in VLSI Design from SASTRA University and a Bachelor of Technology in Electronics and Communications Engineering from Sri Venkatesa Perumal College of Engineering & Technology.