Gyana Pattanaik

Gyana Pattanaik is a seasoned Thin Films Process R&D Engineer at Tokyo Electron US since March 2017, focusing on advanced nodes at TEL Technology Center America. Previously, Gyana held the position of Senior Research Scientist in 3D Interconnects at Atotech Group from December 2012 to February 2017, contributing to the SEMATECH 3D program and dual damascene process development. Prior experience includes research work at the Air Force Research Laboratory on nanostructured materials for lithium-ion batteries, as well as roles at Seagate Technology, Rensselaer Polytechnic Institute, the University of Virginia, Karlsruher Institut für Technologie, and Indian Institute of Technology, Delhi. Gyana holds a PhD in Physics from the Indian Institute of Technology, Delhi, and an M.Sc. in Physics from Utkal University.