Yixuan Huang

Yixuan Huang is an RFIC Engineer Intern at Ubilite since June 2017, focusing on base band PLL design in 28nm technology, specifically addressing phase noise and jitters for Ultra Low Power 802 applications. Previously, Yixuan served as a Teaching Assistant for Analog VLSI at Boston University from September 2016 to January 2017, providing tutorials on Cadence and assisting students with experiments and homework evaluations. Yixuan also completed an internship at Kingdee International Software Group in July 2012, performing system maintenance tasks and gaining foundational knowledge in database maintenance. Yixuan holds a Master of Engineering in Computer Engineering from Boston University and a Bachelor of Science in Microelectronics from Jilin University.