Pavan Kasargod is a Senior Technical Lead with over 15 years of experience in VLSI Physical Design, specializing in high-quality silicon delivery across advanced technology nodes such as 40nm, 28nm, 12nm, and 6nm. Currently, Pavan leads a skilled team at UST Global, focusing on physical design implementation and strategic project execution. Pavan has previously held roles at Qualcomm, Magma Design Automation, and Synopsys Inc., contributing to multiple successful tape-outs through effective design flow optimization and team mentorship. Pavan earned a Bachelor's Degree in Electrical, Electronics, and Communications Engineering from Visvesvaraya Technological University.
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