Raghuraman Ramanathan

Raghuraman Ramanathan has 10 years of work experience. Raghuraman began their career in 2012 as a Teaching Assistant and Tutor for Digital Design at San Jose State University. In 2013, they joined Intel Corporation as a Staff SOC Design Engineer, where they were later promoted to SOC Design Engineer. During their time at Intel, they led a Validation team of 4 Engineers to validate all Boot and Power management flows across different projects, and improved simulation performance efficiency by 20%. In 2023, they joined Ventana Micro Systems as a Senior Staff DV Engineer.

Raghuraman Ramanathan attended San Jose State University from 2012 to 2014. Raghuraman then attended Saranathan College of Engineering and TBHSS, though the duration of their attendance is unknown. In addition, they obtained a PLC certification from Technocrat Automation in June of 2010.