Kumar Vikram

Kumar Vikram has worked in various roles for several companies over the years. In 2021, they began working as a Principal Engineer for Verana Networks. Prior to that, they were a Staff Engineer for Radisys Corporation in 2020. From 2018 to 2016, they worked as a Senior Technical Leader for Altran, where they were responsible for the design and development of L1 software components of key 3gpp NR 5G release 15 and release 16 features. kumar also led feature enhancement and defect corrections of layer one and layer two software components in UE Simulator, TM500. Before that, they worked as a Senior Technical Leader for Azcom Technology from 2016 to 2005. During that time, they designed and developed L1 algorithms for 4G PUSCH processing chain, and enhanced features and fixed critical issues in the different modules of uplink and downlink processing chain of LTE/4G. Additionally, they worked as a Technical Leader and Senior Software Engineer for Aricent Technologies Holdings Limited. (Flextronics Software) from 2005 to 2016. During this time, they were responsible for the design and development of DSP modules of Echo canceller for VQE 3700 product, as well as video streaming on Ethernet and GPRS using TI-OMAP 730 processor. kumar also worked as a Software Engineer for the company.

Kumar Vikram attended Delhi Public School, Ranchi before pursuing a Bachelor of Engineering in Electrical and Electronics Engineering at Birla Institute of Technology, Mesra from 2001 to 2005.