Estell Lopez

Estell Lopez has been a Senior Electrical Design Engineer at Verasonics since 2019. Estell designs FPGA logic in VHDL and Verilog to control acquisition circuits in an ultrasound instrument, as well as logic to communicate with a host computer using PCI express and DDR4 memory. Prior to this, Lopez was a Senior Electrical Design Engineer at Zetec from 1992 to 2019. During this time, they designed non-destructive test (NDT) eddy-current array instruments and peripherals, overseeing product development flow from definition through architecture, design, electronic component selection, board layout guidance, rapid prototyping, testing, programming, debugging, verification, documentation, and manufacturing support. Estell also designed analog and mixed-signal circuits, driving probes and then detecting and amplifying eddy-current signals from sense coils and achieving signal quality improvement of 5 dB over competing instruments. Additionally, Lopez designed electronic hardware for non-destructive testing instruments, including analog/mixed-signal, digital, FPGA, and signal processing, as well as motor control for positioning and rotating probes.

Estell Lopez received a Master of Science in Electrical Engineering (MSEE) from Kansas State University, with a focus in Signal Processing. Estell also obtained a Bachelor of Science in Electrical Engineering (BSEE) from Kansas State University. In addition, they took an Image Processing course at Portland State University.