CM

Catherine McGowan

Design Verification Engineer at Verilab

Catherine McGowan has a diverse work experience in the field of design verification engineering. Catherine began their career at Sun as a contract Design Verification Engineer from June 2005 to March 2008. Catherine then worked at Infinera as a Staff Design Verification Engineer from February 2009 to December 2012, where they served as the verification lead for packet FPGA(s) and developed UVM verification methodology and test bench. Catherine joined RGB Networks as a Design Verification Engineer from 2013 to 2014. Catherine then worked at AMD as a Design Verification Engineer from January 2015 to June 2015, and at HGST as a Design Verification Engineer from June 2015 to April 2016. At HGST, they created, maintained, and augmented the UVM verification environment for an FPGA prototype project and incorporated various VIPs while communicating with the ASIC team. Catherine joined Lockheed Martin as a Design Verification Engineer from April 2016 to February 2017, where they implemented and checked in initial files for an FPGA level UVM testbench. Catherine established the correct bit/byte configuration for all valid frame sizes on XGMII lanes. Catherine then worked at Juniper Networks as a Design Verification Engineer from February 2017 to January 2018, where they created a UVM environment for an IEEE-1588 Precision Time Protocol device and added to a legacy Verilog test bench. Catherine joined Microsoft as a Design Verification Engineer in February 2019 and worked there until June 2020. At Microsoft, they were responsible for architecting and implementing a UVM constrained random environment for a complex proprietary data path in an ASIC, developing components, scoreboards, tests, and test plans. Lastly, they currently work at Verilab as a Design Verification Engineer starting from October 2020.

Catherine McGowan’s education history includes a degree in Electrical Engineering from Old Dominion University. Catherine has obtained both a Bachelor of Science in Electrical Engineering (BSEE) and a Master of Science in Electrical Engineering (MSEE) from this institution. The chronological information does not provide specific start and end years for their education at Old Dominion University.

Links

Previous companies

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Juniper Networks logo
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Timeline

  • Design Verification Engineer

    October, 2020 - present

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