Marko Olujić

Design Verification Engineer at Verilab

Marko Olujić began their work experience in 2009 at HDL Design House, where they served as a Senior Verification Engineer until 2016. In 2016, they joined Verilab as a Design Verification Engineer, where they currently hold a position.

Marko Olujić received their Master of Science degree in Electrical and Computer Engineering from the Faculty of Technical Sciences in Novi Sad. Marko completed their education at this institution from 2001 to 2007.

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