The Verification Engineers at Verilab are dedicated to ensuring the functional integrity of VLSI designs. They employ advanced methodologies and cutting-edge verification tools to address complex challenges, from rescuing failing chip designs to developing robust verification IP. Their expertise spans ASIC and FPGA verification, with a focus on enhancing existing workflows through best practices, ultimately delivering high-quality, reliable semiconductor solutions.
Andre Winkelmann
Principal Verification Enginee...
Bojan Arsov
Verification Engineer
Catherine McGowan
Design Verification Engineer
Damir Ahmetovic
Verification Engineer Consulta...
Ilija Adzic
Design Verification Engineer
Jeff McNeal
ASIC & FPGA Verification Consu...
Marcus Harnisch
Design Verification Engineer
Mark Litterick
Senior Vice President, Verific...
Marko Olujić
Design Verification Engineer
Michael Levin
ASIC/FPGA Verification Enginee...
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