Paweł Kasperski

Paweł Kasperski is the Head of Engineering at Vtool Poland, where they manage verification projects and support the growth of the Polish Department. Previously, they held positions as a Principal IC Verification Engineer at both Synaptics Incorporated and DisplayLink, as well as a Principal Design Engineer and Lead Design Engineer at Cadence Design Systems. Paweł also has experience as a Digital IC Design Engineer and intern at Evatronix, and holds a Master of Science in Electronics and Telecommunication from Silesian University of Technology.