Meng Peun Tan is a seasoned Sr. Process Integration Engineer at WaferTech since January 2017, responsible for managing logic, SRAM, flash, EEPROM, and analog IC products across various technology nodes while ensuring alignment with automotive standards. Prior experience includes serving as a Module & Integration Yield Engineer at Intel Corporation from April 2013 to May 2016, focusing on wafer defect inspection tools for Logic Technology Development. Meng Peun Tan began an academic career as a Graduate Research Assistant at the University of Illinois at Urbana-Champaign, conducting research on semiconductor optoelectronic devices and achieving significant advancements in photonic crystal vertical-cavity surface-emitting lasers. Educational credentials include a PhD, MS, and BS in Electrical Engineering from the University of Illinois at Urbana-Champaign from 2003 to 2013.
Org chart
Sign up to view 0 direct reports
Get started