Jayati Vyas

Jayati Vyas is a Senior Design Verification Engineer at Wipro Limited, bringing 7 years of experience in design verification for leading silicon companies. Jayati completed a Master of Technology in VLSI Design from Banasthali Vidyapith and a Bachelor of Technology in Electronics and Instrumentation from Shri Vaishnav Institute of Technology and Science. Previously, Jayati contributed to projects at Bhabha Atomic Research Centre and served as a Design Verification Engineer at Altran. Jayati began their career as a Trainee Engineer at Maven Silicon, where they developed verification environments using UVM.