Saravanakumar Raja is a skilled RTL Design Engineer with extensive experience in VLSI and ASIC design. They currently serve as a VLSI Technical Lead at Wipro, a position they have held since 2025. Previously, Saravanakumar worked at various companies including VVDN Technologies and Altran, focusing on IP RTL Design for 5G and FPGA RTL Design, respectively. Saravanakumar earned a Bachelor of Engineering in Electronics and Communication from Nandha Engineering College, where they graduated in 2011.
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