Jonathan Alvarez

Jonathan Alvarez is an experienced ASIC/FPGA Verification Engineer at YASKAWA Europe since February 2015, specializing in the verification of complex ASIC designs utilizing UVM constraint random verification standards and improving verification processes and quality. Previous roles include Project Manager for ASIC verification at Ericsson, where Jonathan organized team efforts and developed verification strategies, as well as responsibilities at ST-Ericsson focusing on VHDL development for LTE technology. Jonathan's career began as an ASIC/FPGA Designer at Ericsson and included research and design at Fraunhofer IIS, developing advanced satellite receiver technologies. Jonathan holds a Master’s Degree in Elektrotechnik from Erlangen Fraunhofer IIS/Erlangen University and an Engineer's degree in Electrical, Electronics, and Communications Engineering from Universidad de Las Palmas de Gran Canaria.