Leisheng Gao

Leisheng Gao is a Senior Mixed Signal Design Engineer at Acacia Communications Inc., focusing on high-speed transceiver design since November 2019. Previously, Leisheng worked at TSMC Canada Design Center as a Senior Mixed-Signal Design Engineer, where the design of a SAR ADC in a 56G SERDES was carried out from July 2017 to November 2019. Leisheng also contributed as a Staff Design Engineer and manager at a startup in Vancouver, Canada, engaged in designing synthesizer circuits for Bluetooth from October 2016 to April 2017. Earlier experience includes a position as a Staff Analog Design Engineer and Manager at Marvell Semiconductor from July 2010 to March 2017, where Leisheng designed circuit layouts for SERDES RX components, including CDR and Equalizers. Leisheng holds a Ph.D. in Electrical and Electronics Engineering from the University of Chinese Academy of Sciences, attained from 2005 to 2010, and a Bachelor's degree in Electronic Science and Technology from Tianjin University, completed in 2005.