Amit Madupu

Amit Madupu is a seasoned professional in the field of design-for-test (DFT) with extensive experience across various organizations. Currently serving as a DFT RTL Architect/Sr. Manager at AMD since February 2023, Amit focuses on DFT architecture, RTL design, and ATPG for CPU cores. Prior experience includes roles at Cerebras Systems, where Amit worked on DFX for Wafer Scale Engines, and at Esperanto Technologies, Inc. as DFX Engineering Manager, leading the DFX team. Additional experience encompasses positions as a DFT Architect at Cavium Inc and DFT Lead/Architect at Synopsys. Amit holds a Master of Science in Electrical Engineering from Northern Illinois University and a Bachelor of Engineering in Electronics Engineering from Walchand Institute of Technology, Solapur.