Declan Carey

Declan Carey is currently a Fellow at AMD since July 2023 and has served as a Principal Member of Technical Staff at Xilinx since June 2012, specializing in Gigabit SerDes Transceiver design across multiple fabrication nodes including 20nm planar, 16nm, and 7nm FinFET. Prior roles include Senior Staff Engineer and Staff Engineer, and contributions to the ESSCIRC Technical Program Committee for Wireless and Wireline with leadership positions in sessions at several ESSCIRC conferences from 2019 to 2023. Previously, Declan held the position of Senior IC Designer at Firecomms, focusing on designing a 25Gbps Optical Receiver, and worked as a Senior RF/Analog IC Designer at Freescale Semiconductor, contributing to various analog and RF design projects. Educational qualifications include a BEng in Electrical and Electronics Engineering from University College Cork.