Greg Shieh

Greg Shieh has extensive experience in performance modeling and system architecture, currently serving as the IO Performance Modeling Team Lead at AMD since 2013, where responsibilities include developing IO performance models for various hardware protocols and collaborating with SoC teams. Previously at Huawei Technology, contributions involved developing multi-core scheduling algorithms and designing storage servers. During a tenure at Sun Microsystems, Greg focused on the design and modeling of cache hierarchies and storage server integration. Early career experience at HAL Computer Systems included designing multiprocessor systems and evaluating performance using trace-driven simulations. Academic qualifications include degrees from The George Washington University and Michigan State University.