Hoang Nguyen

Hoang Nguyen is an experienced engineering professional with a strong background in silicon design and verification, currently serving as an MTS Silicon Design Engineer at AMD since January 2022. Prior experience includes roles as a Senior Design Verification Engineer at Xilinx from May 2018 to January 2022 and a Senior Design Verification Engineer at Bridgetek for a brief period in 2017, focusing on developing verification IPs using UVM methodology and conducting IP verification. Earlier in the career, Hoang held a Senior ASIC Design Verification Engineer position at Applied Micro Circuits, tasked with logic verification for advanced SoC designs, and began as a Design Engineer at Renesas Design Vietnam Co., Ltd., where responsibilities included integration and verification of non-CPU IPs. Hoang holds a Bachelor’s degree in Mechatronics from Ho Chi Minh City University of Technology and an MBA from CFVG.