Jae Min Park

Jae Min Park is an accomplished engineer specializing in silicon design and analog/mixed-signal circuits. Currently serving as an SMTS Silicon Design Engineer at AMD since June 2022, Jae Min previously held the position of Senior Staff Design Engineer at SK hynix memory solutions inc. from December 2016 to June 2022, leading RX design efforts in high-speed logic library and Serdes Receiver design. Prior experience includes a role as Senior Analog Design Engineer at Marvell Semiconductor from August 2011 to December 2016, where Jae Min focused on designing Continuous-Time Linear Equalizers and high-speed front-end circuits. Jae Min holds a Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science in Electrical and Electronics Engineering from Yonsei University.