Jayalakshmi C

Jayalakshmi C is a seasoned engineer with extensive experience in DFT and SOC design, currently serving as a Staff DFT Engineer at AMD since February 2022, while also holding the same title at Xilinx since October 2018. Previous experience includes a role as a SOC Design Engineer at Intel Corporation from December 2015 to September 2018, where significant contributions were made in validating CPU and SOC features for 10nm projects. Jayalakshmi has a strong background in developing and implementing testing frameworks using System Verilog and Perl, alongside expertise in validating complex functional designs in graphics hardware at Intel Corporation from May 2011 to October 2015. Education includes an MTech in VLSI & Microelectronics from the National Institute of Technology Calicut and a BTech in Electronics & Communication from Mahatma Gandhi University.