Shahar G.

Shahar G. is an experienced engineering professional specializing in pre and post silicon SoC validation, currently serving as an MTS Pre and Post Silicon SoC Validation Engineer at AMD since March 2022. Prior to this role, Shahar worked as a Post Silicon ASIC Validation Engineer at Semtech from February 2018 to March 2022, focusing on the development and execution of ASIC validation plans utilizing LabVIEW and Python, along with automation tools. Shahar's earlier experience includes a position as a Hardware Manufacturing Specialist at Intel Corporation from October 2007 to January 2011, where responsibilities included maintenance, calibration, and troubleshooting of microprocessors manufacturing tools. Shahar holds a Bachelor's degree in Electrical and Electronics Engineering from Concordia University (2011-2017) and an Electronic Technologist degree from ORT Colleges (2003-2005).