Alessandro Locardi

Alessandro Locardi is a seasoned Principal Digital Verification Engineer currently leading the DV Team at Allegro MicroSystems, focusing on high-performance power group initiatives since May 2023. With extensive expertise in verification planning, UVM using SystemVerilog, assertion-based verification, and formal verification, Alessandro has previously contributed to NXP Semiconductors and STMicroelectronics, honing skills in automotive functional safety and low power design. Academic credentials include a Master of Engineering from Università di Pavia and a Bachelor's degree in Electronic Engineering, complemented by early training in informatics. Proficient in various tools and environments, including Cadence and Siemens platforms, Alessandro demonstrates a strong background in managing DV resources and projects while enhancing methodologies for verification flows.