Nikita Litvishko

Nikita Litvishko is a Digital Verification Engineer at Allegro MicroSystems since January 2023, with prior experience as a Digital Design Engineer at Renesas Electronics from September 2021 to December 2022, where responsibilities included digital design in Verilog and digital verification using UVM. Nikita started as a Junior Digital Design Engineer at Renesas after the acquisition of Dialog Semiconductor, initially working on digital design and verification at Dialog Semiconductor from September 2020 to August 2021. Previous roles include FPGA Design Engineer at Cegelec a.s., where responsibilities involved electric motor control system implementation and PCB design, as well as a Diploma Student at Adesto Technologies, focusing on SoC design and verification tasks. Nikita’s academic background includes a Bachelor's degree in Cybernetics and Robotics and a Master's degree in Electrical, Electronics, and Communications Engineering, both from the Czech Technical University in Prague.