Uriel Padilla

Uriel Padilla is a Digital Physical Design Engineer and Layout Engineer at Allegro MicroSystems since March 2020, bringing valuable experience from a previous role as a software developer at Atix Labs from August 2018 to February 2020. Uriel holds a degree in Ingeniería Electronica from Universidad Tecnológica Nacional, obtained in 2019, and completed a Bachillerato En Ciencias Naturales at Colegio Nuestra Señora de Lourdes in 2012.