Naveen Bharathwaj Akesh

Naveen Bharathwaj Akesh is an experienced FPGA Circuit Design Engineer currently at Altera since August 2025, following a prominent tenure at Achronix Semiconductor Corporation from November 2017 to July 2025, where roles included Principal Engineer and Senior Hardware Engineer. Prior to Achronix, Naveen worked at Oracle as a Senior Hardware Engineer from June 2014 to October 2017, contributing significantly to projects involving statistical analysis and hardware design. Early experience includes a research assistant position at the University of Michigan from May 2013 to April 2014, focusing on configurable memory and innovative book technology projects. Naveen earned a Master’s Degree in VLSI from the University of Michigan and a Bachelor’s Degree in Electrical, Electronics and Communications Engineering from Anna University Chennai.