Anand Thibbaiah

Anand Thibbaiah has a diverse work experience in the field of physical design engineering. Anand currently holds the position of Principal Physical Design Engineer at Ampere since August 2021. Prior to this, they worked as a Senior Staff Physical Design Engineer and Staff Engineer at the same company. Anand also has experience as a Senior Design Engineer at Ampere and AppliedMicro. Anand began their career as an ASIC Trainee at RV-VLSI Design Center, where they gained expertise in various aspects of chip implementation. Anand also served as a Project Intern at United Telecoms Limited, where they developed an IP core for STM-1 framer using Verilog HDL.

Anand Thibbaiah completed their Master of Technology degree in VLSI Design and Embedded Systems from VTU Extn Centre, UTL Technologies, during the years 2010-2012. Prior to that, they obtained a Bachelor of Engineering degree in Telecommunication from Acharya Patashala College of Engineering (2004-2008). Anand completed their PU studies in Electronics at PES PU College from 2003-2004. In 2001-2002, Anand attended Bangalore High School, focusing on the field of Physics.