Martin S.

Martin S. has extensive experience in design engineering, currently serving as a Principal Design Engineer at Aptina Imaging since January 2009, focusing on RTL design, verification, and prototyping for Sensor On Chip designs. Prior to this role, Martin S. spent over a decade at Micron Technology as a Principal Design Engineer, where contributions included the development of 32-bit RISC processors for 3D graphics. Martin S. began the career at LSI Logic as a Senior Design Engineer, contributing to the OAK DSP core and customer demonstration chip. Earlier experience includes roles at GPT Ltd and GEC, where Martin S. worked on ASIC projects and telecommunications equipment. Education culminated in a Bachelor of Engineering from Coventry University, complemented by an OND from Coventry Technical College in Telecommunications and Electronic Engineering.