Zaka Ur Rahman

Zaka Ur Rahman is a Design Verification Engineer at Aql Tech Solutions (Pvt) Limited since November 2021, specializing in the verification of ACE and AXI based compute Cache Coherence Blocks on Akeana's project. Responsibilities include updating the UVM-based testbench environment, debugging and reporting RTL issues, implementing functional cover points, and performing gate level simulations. Previously, Zaka served as an Associate Design Verification Engineer at Lampró Méllon, leading the IP onboarding team and working on the verification of Synopsys peripheral IPs. Initial experience included a role as a Graduate Engineering Trainee focused on digital design and verification in Verilog/SystemVerilog. Zaka holds a Bachelor's degree in Electrical and Electronics Engineering from the University of Engineering and Technology Taxila and completed FSc in Pre-Engineering at F.G Degree College for Men Wah Cantt.