Shabarish V

Shabarish V is a Senior CPU Design Verification Engineer at Arm, where they are part of a dedicated team focusing on the integrity and performance of next-generation processors. With a Bachelor of Engineering in Electronics and Communications Engineering from Visvesvaraya Technological University, Shabarish leverages expertise in Universal Verification Methodology (UVM) and SystemVerilog to drive innovation in CPU design verification. Previously, they were a Senior Design Verification Engineer at Wipro, contributing to Intel's IPU/DPU design verification and developing test benches for unit and block level design. Shabarish also gained experience in the telecom sector while working with BSNL, where they applied their skills in 3G and 4G network systems.