Arteris
Benjamin Madon has a varied work history, starting with their current role as a Hardware Design Engineer at Arteris IP since 2021. Prior to that, they worked as a Postdoctoral Researcher at the IBM Almaden Research Center from 2017 to 2021. Benjamin also served as a PhD candidate at Ecole Polytechnique from 2014 to 2017, where their research focused on studying the Righi-Leduc effect in ferromagnetic thin films. Benjamin also had a role as a Research Intern at Ecole Polytechnique in 2014, where they measured the thermoelectric properties of a bismuth electrode on ferromagnetic thin films. In addition, they worked as a Visiting Grad Student at the University of California, Riverside in 2015, conducting spin Hall magnetoresistance measurements. Benjamin's work experience also includes a research internship at IBM Almaden in 2013, where they studied the effect of vanadium oxides phase transition on the properties of metallic ferromagnetic thin films. Prior to their research roles, Benjamin worked briefly as a Quality Control Assistant at Saint-Gobain in 2012.
Benjamin Madon completed their education at École Polytechnique, where they pursued a Master of Engineering (MEng) degree specializing in Electrical Engineering/Physics. This program took place from 2010 to 2014. Afterward, they continued their studies at the same institution and obtained a Master of Science (MSc) in Physics from 2013 to 2014.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.