Gabriel Busnot

Staff Performance Modelling Engineer at Arteris

Gabriel Busnot has a diverse work experience. Gabriel is currently working at Arteris IP as a Staff Performance Modelling Engineer since March 2022. Prior to this role, they held the position of Senior Performance Modelling Engineer at Arteris IP from October 2020 to February 2022. Gabriel also worked at CEA as a Doctorant from October 2017 to October 2020 and as a Stagiaire from April 2017 to October 2017. Gabriel gained further experience as an Étudiant at ENSTA ParisTech - École Nationale Supérieure de Techniques Avancées from September 2014 to July 2017. Additionally, Gabriel had a research project at Högskolan i Halmstad where they worked for three months in the development team of Acumen, a rigorous hybrid system simulation software. Gabriel was involved in developing functionalities related to probability distributions. Furthermore, Gabriel had a one-month internship at Caritas Novossibirsk, where they volunteered and worked on restoration projects in the association's facilities.

Gabriel Busnot completed their education history as follows:

From 2014 to 2017, Gabriel attended ENSTA Paris where they earned a Diplôme d'ingénieur in Systèmes embarqués.

Following that, from 2017 to 2020, Gabriel pursued their Doctorat in Informatique at Université Claude Bernard Lyon 1.

Before their enrollment at ENSTA Paris, Gabriel attended Lycée Clemenceau - Prépa MPSI - MP* from 2012 to 2014, where they studied Math, physique, and Info. It is not specified whether they obtained a degree from this institution.

Additionally, in March 2020, Gabriel obtained a certification in Introduction to FPGA Design for Embedded Systems from Coursera.

Location

Paris, France

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Arteris

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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.


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201-500

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