Hema Sajja

Hema Sajja has a significant amount of work experience in the field of design verification engineering. Starting in 2011, they worked as an EOS Help-Desk Consultant at ITECS Engineering Labs for NC State University for seven months. From 2012 to 2016, Hema Sajja was a Design Verification Engineer in the Mobile CPU Design/Verification Team at Qualcomm, where they were responsible for block-level verification of high-performance ultra-low power ARM architecture-based Snapdragon microprocessors. In 2016, they briefly worked at Intel Corporation as a Pre-silicon Verification Engineer, focusing on the validation of microcode flows in the Intel Atom-CPU. From 2017 to 2018, they worked as a Senior DV Engineer at Qualcomm, specializing in unit-level verification of last-level L3 cache for server CPU/SOC. Finally, in 2018, Hema Sajja joined Arteris IP as a Hardware Verification Engineer, and later progressed to the roles of Senior Design Verification Engineer and Staff Design Verification Engineer.

Hema Sajja began their education in 2006 at Jawaharlal Nehru Technological University, where they earned a Bachelor's degree in Electronics and Communication Engineering in 2010. Following their undergraduate studies, they attended North Carolina State University from 2010 to 2011, obtaining a Master of Science degree in Computer Engineering.