Fengkai Bao

Fengkai Bao is an experienced Senior Staff ASIC Design Verification Engineer at Marvell Technology, with a career that includes significant roles at ASML as a Senior FPGA Design Engineer and FPGA Design Engineer, where responsibilities included designing customized FPGA modules and developing SPI interface drivers for various DAC/ADC devices. Prior experience includes serving as a Teaching Assistant at the UM-SJTU Joint Institute, interning at Boeing Shanghai Aviation with a focus on wireless equipment for aircraft, and assisting in program management at AVIAGE SYSTEMS. Fengkai Bao holds a Master's degree in Electrical Engineering from the University of Southern California and a Bachelor's degree in Electrical and Computer Engineering from the UM-SJTU Joint Institute.