Arteris
Jean-Philippe Sibers has a diverse work experience in the technology industry.
Jean-Philippe is currently serving as the Vice President of Engineering at Arteris IP since 2022.
Before that, they worked at JCDecaux as the Group R&D Director from 2019 to 2022. In this role, they were responsible for defining and managing the R&D investment roadmap. Jean-Philippe also headed the engineering team developing JCDecaux street furniture and associated services, managing a budget of 19M€ and a team of 200+ engineers and technicians across multiple countries. Jean-Philippe implemented change management strategies to improve internal development capabilities and performance, including product life cycle definition, organizational change, and staff renewal.
Prior to JCDecaux, Jean-Philippe worked at Atos from 2014 to 2019. Jean-Philippe held multiple positions during their tenure, including R&D Director, Head of Servers Design, Atos Distinguished Expert - Hardware and Firmware Experts Domain Leader, and Atos Scientific Community Member. As R&D Director, they led an engineering department responsible for developing servers for Bull trademark, managing a budget of 17-20M€ and a team of 190+ engineers across different countries. Jean-Philippe also played significant roles in Atos' innovation strategy for IT infrastructures and collaborated with the Expert Community and Scientific Community to shape the company's future vision and technology roadmap.
Before joining Atos, Jean-Philippe was the Electronics Engineering Manager at Bull from 2010 to 2014. Jean-Philippe led the EE department and was responsible for developing electronic boards for high-performance computing and datacenter servers.
Jean-Philippe also has experience working at SAGEMCOM as a Project Manager in 2010 and at DiBcom as a Co-founder and in various roles from 2000 to 2010. At DiBcom, they played a key role in the creation and development of the semiconductor start-up, raised significant venture capital funds, and successfully pivoted the company's business focus over the years. Jean-Philippe managed R&D programs, led hardware reference designs, and served as an ASIC design project leader and engineer.
Overall, Jean-Philippe Sibers has a strong background in engineering, R&D management, and strategic leadership, with experience in various technological domains and international teams.
Jean-Philippe Sibers obtained their Diplôme d'ingénieur from École Polytechnique, where they studied from 1996 to 1999. This program did not specify a field of study. In 1999, they pursued an MSc in Integration, Circuits and Systems at Télécom Paris, completing the degree in 2001.
In 2016, Jean-Philippe attended HEC Paris for an executive education program in Business Administration called the Atos Gold for Managers Program. This program did not specify a degree name, but it focused on the field of study of Business Administration.
Furthermore, Jean-Philippe has obtained various certifications in the field of machine learning and deep learning. These certifications include Deep Learning Specialization from DeepLearning.AI, Sequence Models from DeepLearning.AI, Machine Learning from Stanford Online, Convolutional Neural Networks from DeepLearning.AI, Improving Deep Neural Networks: Hyperparameter Tuning, Regularization and Optimization from DeepLearning.AI, Neural Networks and Deep Learning from DeepLearning.AI, and Structuring Machine Learning Projects from DeepLearning.AI. Jean-Philippe obtained these certifications between 2021 and 2022.
This person is not in any offices
Arteris
2 followers
Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.