Arteris
Tim S. has held various roles in the field of application engineering and electronics engineering throughout their career. Tim started their career at Boeing in 1988 as an Electronics Engineer, specializing in embedded software development for avionics systems. Tim then joined Honeywell in 1990 as a Senior Electronics Engineer, where they worked on FPGA design and ASIC development for industrial automation products.
In 1995, Tim S. began working at Synopsys Inc. as a Sr. Application Engineer in the Southwest Region, focusing on verification products. Tim supported customers and account managers across multiple states, leading successful sales campaigns and receiving recognition for their outstanding contributions. Tim remained with Synopsys Inc. until 2018, working in various roles including Field Applications Engineering - Senior Staff and Application Consultant.
In 2019, Tim S. joined JADAK Tech as an Application Engineer, providing technical consultation and delivering product demonstrations in the medical device industry. Tim also developed project proposals and supported account management teams during pre-sales and prototype project phases.
Most recently, in 2021, Tim S. joined Arteris IP as a Senior Application Engineer. Further information about their role at Arteris IP is not provided.
Tim S. obtained a Bachelor's of Science degree in Electrical, Electronics, and Communications Engineering from Wichita State University. In addition, they have earned several certifications. In June 2017, they obtained the SemiConductor Automotive Functional Safety Professional (SC-AFSP) certification from SGS-TÜV Saar. Tim also holds three verified certificates from edX: Fundamentals of TinyML (August 2021), Applications of TinyML (September 2021), and Deploying TinyML (March 2022).
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Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.