Zied Tlili

Zied TLILI has a diverse work experience in the field of design verification engineering. Zied currently holds the role of Senior Design Verification Engineer at Arteris IP, where they began working in January 2021. Prior to this, Zied worked at Nokia from November 2017 to January 2021 as a 5G SoC/FPGA Verification Engineer. In this role, they were responsible for the verification of the 5G Layer-1 Downlink IP (Tx) and led the DL environment verification. Zied also implemented and updated scalable and generic VIPs and environment using SystemVerilog and UVM. Before joining Nokia, Zied worked as a Stagiaire in ASIC verification at Atos from April 2017 to October 2017, where they were involved in adopting the UVM methodology for verification. Zied's earlier experience includes working on the conception and integration of an acquisition module in an embedded system at the laboratoire d'électronique et d'électromagnétisme (UPMC) & EDF in 2016.

Zied TLILI began their education by completing their Baccalauréat degree in Mathematics at Lycée Hamida Bkir Ariana. Afterwards, they attended Institut Préparatoire aux Etudes d'Ingénieurs de Tunis from 2012 to 2014, where they pursued studies in Mathematics and Physics. Subsequently, Zied enrolled at ENSTA Paris from 2014 to 2017, obtaining a Diplôme d'ingénieur in Embedded Systems.