Malavikka Ramesh

Malavikka Ramesh is a skilled engineer with extensive experience in pre-silicon and post-silicon validation within the semiconductor industry. Currently serving as a Member of Technical Staff at Astera Labs since September 2021, Malavikka focuses on validating the performance throughput of complex I/O IP to meet PCIe Gen5 bandwidth requirements. Prior experience includes working as a Pre-Silicon Verification Engineer at Intel Corporation, where responsibilities included developing validation test plans for Hot-Plug logic and ensuring optimal chip performance through various validation techniques. Malavikka's career began with positions at Oracle, where validation of timers and error units was undertaken, and as a Teaching Assistant at the University of California, Santa Barbara. Malavikka holds a Master of Science in Computer Engineering from UCSB and a Bachelor of Engineering in Electrical and Electronics Engineering from Anna University.