Manish Ladani

Manish Ladani is a seasoned ASIC Verification Engineer with extensive experience in the semiconductor industry. Currently serving as a Member of Technical Staff at Astera Labs since November 2021, Manish previously held the position of Sr. Pre-Silicon Design Verification Engineer at Intel Corporation from December 2019 to November 2021. Manish began a career at eInfochips in May 2007 as a Member of Technical Staff, specializing in ASIC design and verification as well as embedded systems software. Expertise includes HDL and HVL programming in Verilog/System Verilog, utilizing UVM verification methodology, and working with protocols such as NVMe, AXI, LPDDR, and Ethernet. Manish is also involved in the creation of architecture for Verification IPs and Verification Environments. Educational credentials include a Master’s degree in Electronics and Communication from L.D. College of Engineering and Gujarat University, completed between 2005 and 2007.