Saravanan Kalinagasamy

Saravanan (Saro) Kalinagasamy is a seasoned professional in the semiconductor industry, currently serving as Senior Director of ASIC Design Verification and Validation at Astera Labs. With a robust background in engineering, Saravanan has previously held the position of Senior Director of Engineering for SoC Design Verification and Validation at Aeva. Prior experience includes serving as Director of Engineering for SoC Functional and Performance Verification at Xilinx and as Senior Manager of ASIC Design Verification at SanDisk.