Egor Smirnov

Egor Smirnov has been working in the technology industry since 2013. Egor started as an RnD Engineer at Владимирское Конструкторское Бюро Радиосвязи in 2013, then moved to Garant Plus as an FPGA designer in 2014. In 2015, they joined Aquantia as an FPGA Design Engineer, where they were responsible for FPGA prototyping, RTL verification, and RTL design using Verilog and SystemVerilog HDL languages and Xilinx FPGA ultrascale+ family. Egor then became a FPGA Team Lead at Marvell Technology in 2018, before joining Aviva Links as an ASIC Design Engineer in 2020.

Egor Smirnov attended Vladimir State University from 2005 to 2014, where they earned a Magister degree in Radio and Television.