Jean-Yves Simon

Jean-Yves Simon is a highly experienced engineer specializing in ASIC design and verification, currently serving as Principal ASIC Design and Verification Engineer at PROPHESEE since September 2022. Prior roles include ASIC Design and Verification Engineer at CEVA, Inc. from March 2021 to August 2022, and Technical Leader for FPGA/ASIC at Nokia from November 2017 to February 2021, where notable contributions were made to 5G mobile networks. Earlier experience includes mixed-signal design at NXP Semiconductors and various leadership roles in IP design at Texas Instruments across multiple international sites. Academic credentials include engineering studies at Télécom Paris and a Bachelor and Master in Physics from Université de Bretagne Occidentale.