Jaya Vardhan Ponnala

Jaya Vardhan Ponnala has worked as a Design Verification Engineer for Aviva Links since 2022. Prior to this, they worked as an ASIC Verification Engineer at onsemi since 2022. Before that, they were an RTL Design & Verification Engineer at Maven Silicon from 2021.

Jaya Vardhan Ponnala attended CVR College of Engineering, Hyderabad from 2017 to 2021, where they obtained a B.tech in Electronics and Communications Engineering.