Antoine Madec

Antoine Madec is currently working as an Engineering Manager - Silicon Verification at Axelera AI. Prior to this role, Antoine served as a Staff Verification Engineer at Elsys Design and as an ASIC Verification Tech Lead at DinoPlusAI. Antoine has also held positions at Cadence Design Systems, Ambarella Inc, and Sigma Design Inc. Antoine specializes in ASIC verification, including block-level and top-level verification, system-level verification, and FPGA development. Antoine holds a Master’s Degree in Electrical and Electronics Engineering from Illinois Institute of Technology and an Engineer’s Degree from ENSEIRB-MATMECA.